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alsa-utils/topology/nhlt/intel/ssp
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Seppo Ingalsuo 0c780e1fa0 Topology: NHLT: Intel: SSP: Handle differences for ACE3.x 
- The SSC1 bits 21 and 20, TSRE and RSRE, do not exist.
- The SSC0 bit 30 ACS does not exist.
- The SSC0 bit 6 ECS does not exist but needs to be set, add note.
- The MDIVXCTRL bits 20:21 MNDSS does not exist.

Closes: https://github.com/alsa-project/alsa-utils/pull/276
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
2024-10-23 13:01:07 +02:00
..
ssp-debug.c Topology: NHLT: Intel: SSP: Add support for blob format 2024-10-23 13:01:07 +02:00
ssp-debug.h topology: plugins - add Intel nhlt encoder plugin 2022-05-03 13:24:03 +02:00
ssp-intel.h Topology: NHLT: Intel: SSP: Add support for blob format 2024-10-23 13:01:07 +02:00
ssp-internal.h Topology: NHLT: Intel: SSP: Add support for blob format 2024-10-23 13:01:07 +02:00
ssp-process.c Topology: NHLT: Intel: SSP: Handle differences for ACE3.x 2024-10-23 13:01:07 +02:00
ssp-process.h topology: nhlt: intel: support more device types and directions 2023-08-01 09:43:17 +02:00